489-P5-HI-A20-T-H Brad Seo, Vice President of SAPEON Korea Research and Development Center, said: “nepes is committed to providing customers with comprehensive semiconductor package design and manufacturing service solutions to help customers achieve sustained success in the semiconductor market. “In today’s semiconductor industry, where performance and small size are increasingly demanded, the collaboration between nepes and Siemens EDA will help us achieve the innovative technologies we need to grow.”

nepes is a global leader in outsourced semiconductor Package and Test services (OSAT), providing world-class packaging, test and semiconductor assembly services to customers in the electronics industry worldwide. nepes also offers package design services, including wafer-level packaging, fan-level pac489-P5-HI-A20-T-H kaging and panel-level packaging.

Based on existing technologies, nepes joins Siemens EDA’s Calibre® 3DSTACK, HyperLynx™ for electrical rule inspection, And the Xedition™ Substrate Integrator and Xpedition™ Package Designer range of technical capabilities to drive packaging technology innovation and provide fast and reliable design services to IC customers worldwide. In489-P5-HI-A20-T-H cludes chiplet design based on 2.5D/3D.