489-P5-LO-A20-TThe MYD-YD9360 development board adopts the structure of core board and bottom plate. The core board is based on the chip of Xinchi D series. The whole core module is covered with heat sink (the heat sink has been removed in the figure). The bottom plate is mainly an extension of the functional interface, which can be used to evaluate the core board, and can be directly used for prototype product development and design. The official introduction is to support three screen display, which can be used directly as a commercial display board.
Remove the heat sink of the core board, you can see the core module MYC-YD9360 designed by Mill Technology, the module adopts a high-density high-speed 12-layer circuit board design, with 324PIN pin, very compact and compact. Although the size is only 52mm*50mm, there are many integrated devices, including Chipchi D9-PRO series processors, power supplies, LPDDR4, eMMC, EEPROM and other circuits. And relying on the ultra-integrated vehicle level processor D9360, the module has also expanded a wealth of high-speed interfaces, including: USB3.0, PCIe3.0 and Gigabit Ethernet TSN; A wide range of industrial communication interfaces including CAN-FD, UART, I2S, I2C and SPI
In addition, as the core module equipped with the most i489-P5-LO-A20-Tmportant vehicle level processor D9360, from the hardware function diagram inside the chip can be seen that the function is quite rich:
Integrates 6 ARM Cortex-A55, ARM Cortex-R5, NPU, GPU, VPU, and includes commonly used peripheral interfaces, PCIe3.0, USB3.0, 2x Gigabit TSN Ethernet, 4xCAN-FD, 16xUART, SPI, etc. Therefore, it can be seamlessly applied to a variety of industrial applications at the lowest cost, such as a new generation of power intelligent equipment, industrial Internet equipment, industrial control equipment, industrial robots, construction machinery, rail transit, vehicle display, etc.
03 Yicon LogicLab solution is based on STM32MP135 platform
Yicon Technology and STM32 jointly developed and completed the adaptation of LogicLab solution to STM32MP135 processor, including IEC61131-3 standard PLC operating system, Modbus protocol stack, CANopen master protocol stack, EtherCAT master protocol stack, motion control and other components.
At the same time, the Eclipse ThreadX real-time operating system adaptation of STM32MP135 processor and BSP driver are enhanced for PLC applications. After detailed testing, the performance of LogicLab solutions based on STM32MP135 platform has reached the advanced level, and the key technical parameters are as follows:
PLC memory: program area: 16MB, data area: 32MB, p489-P5-LO-A20-Tower down holding area: 128KB
PLC basic instruction execution performance: 4ns
PLC high-speed IO interrupt response capability: <1us
PLC interrupt task response capability: <10us
Recommended minimum cycle for EtherCAT master (DC on): 250us(less than 8 slave stations), 500us(less than 16 slave stations), 1ms(less than 32 slave stations)
Time deviation between EtherCAT task and DC slave station: <10us
Maximum number of axes for motion control :40 axes (including pulse axis and virtual axis)
