JETNET3008F-S IP reuse and modularity help to improve quality and save time, so there is a growing need to integrate off-the-shelf design IP in next-generation semiconductor designs. To ensure the success of silicon wafers, all IP needs to be validated early in the design process to ensure correctness and consistency; If the problem is discovered late in the design cycle, it can lead to a costly flow sheet revision or wafer redesign.
Design IP can be described in detail in multiple design views such as logical, physical, electrical, timing, and power analysis environments, but if the IP is to be fully validated across all of these angles and formats, it can consume significant time and cause delays in production planning.
The Solido IP Verification suite provides production and integration teams with customizable, automated IP verification capabilities that help significantly reduce planning delays. The suite includes Siemens’ Solido™ Crosscheck™ software and Solido™ IPdelta™ software, both of which provide complete IP QA checks for JETNET3008F-S all types of designs and base IP. Integrate in-view QA checks, cross-view QA checks, and version-to-version QA checks in one simplified solution. Solido IP Verification Suite provides IP production and integration teams with fast full process coverage QA through advanced features such as intelligent resolution of IP data reuse, enhanced IP QA for automatic change identification and consolidation of QA reports, and seamless integration with verification platforms such as Siemens Calibre®.
Amit Gupta, Vice President of Digital Industrial Software and General manager of Custom IC Verification at Siemens, said: “With the increasing importance of design IP in the field of semiconductor design, efficient and correct IP verification becomes a crucial step for the success of silicon wafers. “Solido IP Validation Suite provides scalable, reusable solutions for identifying and preventing issues that can cause design disruptions, helping IP production teams achieve high-quality IP delivery with each iteration, helping chip-level design teams accelerate their fluidic plans, and providing qualified and easier to integrate design IP.”
Solido IP verification suite is approved by multiple customers
“Renesas’ memory IP supports many different operating conditions,” said Shuji Katayama, JETNET3008F-S principal EDA Engineer, Digital Back-end Design Methodology, Renesas’ EDA Business Unit. “To quickly ensure the reliability of these memory ips, we deployed Siemens’ Solido IP Validation suite, which can be easily customized to meet our specific needs and improve the quality of memory ips.”
Ming Fatt Yee, design Automation Engineer at Maxlinear, said: “Siemens’ Solido IP verification suite provides a complete QA solution with powerful cross-view checks that simplify and improve QA efficiency, and is user-friendly. “Solido IP validation solutions provide the precision necessary for library deliverables and the customisation capabilities to meet our need for customization.”
“Solido IP Verification Suite provides a range of market-proven verification capabilities that enable QA teams to achieve higher levels of coverage while allowing development teams to get more done in less time,” said Mixel, Inc. “This solution has become an integral part of our QA methodology, giving us the confidence to create differentiated end products,” said Amr Shehata, CAD Manager at the company.
“Solido Crosscheck takes advantage of a full suite of production-oriented customizable IP validation checks to ensure both complete coverage and consistency across IP views,” Rivos Inc. “The Solido IP Verification suite is a key part of Rivos’ IP QA methodology, allowing us to ensure that IP issues are detected early and that the final design meets high QA targets,” said Hema Ramamurthy, head and manager of custom circuits at Rivos.
